Editing RISC-V (section)

==Op Codes==
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* "All the 32-bit instructions in the base ISA have their lowest two bits set to 11" - Spec
 xxxxxxxxxxxxxxaa 16-bit (aa != 11)
 xxxxxxxxxxxbbb11 32-bit (bbb != 111)
 xxxxxxxxxx011111 48-bit
 xxxxxxxxx0111111 64-bit
 xnnnxxxxx1111111 (80+16*nnn)-bit, nnn != 111
 x111xxxxx1111111 Reserved for ≥192-bits

Table 9.1 on page 53 has the opcodes.
"In the base ISA, there are four core instruction formats (R/I/S/U), as shown in Figure 2.2. All are
a fixed 32 bits in length and must be aligned on a four-byte boundary in memory. An instruction
address misaligned exception is generated on a taken branch or unconditional jump if the target
address is not four-byte aligned." - Spec (2.2)

* R-type

  31        25 24     20 19     15 14  12 11      7 6           0
 +------------+---------+---------+------+---------+-------------+
 | funct7     | rs2     | rs1     |funct3| rd      | opcode      |
 +------------+---------+---------+------+---------+-------------+

* I-type

  31                  20 19     15 14  12 11      7 6           0
 +----------------------+---------+------+---------+-------------+
 | imm                  | rs1     |funct3| rd      | opcode      |
 +----------------------+---------+------+---------+-------------+

* S-type

  31        25 24     20 19     15 14  12 11      7 6           0
 +------------+---------+---------+------+---------+-------------+
 | imm        | rs2     | rs1     |funct3| imm     | opcode      |
 +------------+---------+---------+------+---------+-------------+

* U-type

  31                                      11      7 6           0
 +---------------------------------------+---------+-------------+
 | imm                                   | rd      | opcode      |
 +---------------------------------------+---------+-------------+

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