Editing RISC-V

[https://github.com/ucb-bar/riscv-sodor/blob/master/src/common/instructions.scala Instructions in binary]

[http://www.slideshare.net/mdecky/porting-helenos-to-riscv Porting HelenOS to RISC-V]

[https://www.imperialviolet.org/2016/12/31/riscv.html ImperialViolet: RISC-V assembly]

=Minimum Sized ISA=
===Tiny RISC-V===
[http://www.csl.cornell.edu/courses/ece4750/handouts/ece4750-tinyrv-isa.txt Tiny RISC-V only supports 4B signed and unsigned integer values. There are no byte nor half-word values and no floating-point.]

"Tiny RISC-V only supports a 1MB virtual memory address space from 0x00000000 to 0x000fffff. The result of memory accesses to addresses larger than 0x000fffff are undefined."

===Xcondensed===
* [https://docs.google.com/spreadsheets/d/1rray4sbhGarasDS6acnWyAlOjLvDqBXX3s1LrBLtFs8/edit#gid=1499769591 Google Doc of Instructions...]

* [https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/iK3enKGb5bwProposal: Xcondensed, an alternative for Compact that can be used as 16 bit standalone G-ISA]

* [https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/j2okI7akT74 Post about it]

===RISC-V Compressed===
This is intended to be used with the 32bit ISA. Would it work standalone?

"The optional compressed 16-bit instruction format mostly only accesses 8 registers and hence can
provide a dense instruction encoding"

===RV32E===
RV32E is the embedded extension that lowers from 32 registers to 16...

"RV32E uses a subset of the Soft-Float calling convention. As only 16 integer registers x0–x15 are present, there are only six argument registers (x10–x15), two saved registers (x8–x9), and three temporary registers (x5–x7). The stack is kept aligned on a four-byte boundary."

"RV32E uses the same instruction set encoding as RV32I, except that use of register specifiers
x16–x31 in an instruction will result in an illegal instruction exception being raised."

"A further simplification is that the counter instructions (rdcycle[h],rdtime[h], rdinstret[h])
are no longer mandatory."

"The mandatory counters require additional registers and logic, and can be replaced with more
application-specific facilities."

==Registers==
* R32, 5-Bits specify register. 32 registers
* 4-bits will get you 16 (12)
* 3-Bits will get you 8 (4)
* 2-Bits will get you 4 (0) - Similar to a 8bit cpu... But the regs are all used...

* Some registers are fixed though. R0 is always zero, XLEN-1 (last reg) is PC. x1 return. x4-thread pointer might be dropped.

With only 8 registers, could save 2 bits...? Except missing some of the registers are specified in the calling conventions... x8, x9, x10, x11, x12-17 Are the calling conventions actually needed?

Could some of the argument registers be reused?

"There is no hardwired subroutine return address link register, but the standard software calling convention
uses register x1 to hold the return address on a call.": Sounds like a yes to me.

Could consider dropping a register from the instructions and using a fixed one. For example all destinations or sources the same (or each instruction has a specific one...). There are no registers that are common across all instructions. rs1 and rd are in 4 of the formats.



Could drop all register->register instructions and only do memory->register and fixed register?

Some instructions might not specify registers? Might need to reduce maximum number sizes in other fields...

===UJ-type (unconditional jumps)===
UJ-type format, where the J-immediate encodes a
signed offset in multiples of 2 bytes. The offset is sign-extended and added to the pc to form the
jump target address. Jumps can therefore target a ±1 MiB range. JAL stores the address of the
instruction following the jump (pc+4) into register rd. The standard software calling convention
uses x1 as the return address register.

1Mib is excessive...

===SB-type (jumps)===
Doesn't need a dst register (since it's changing the PC), but uses it for the offset. So it would need to be shortened if the registers are...

"All branch instructions use the SB-type instruction format. The 12-bit B-immediate encodes signed
offsets in multiples of 2, and is added to the current pc to give the target address. The conditional
branch range is ±4 KiB"

4kib is excessive. Drop at least the 2-3bits from the size of rd. Could also use multiples of 4 or something...

===Load and Store Instructions===
Loads are encoded in the I-type format and stores are S-type.

rs1 used for the 'base'.

The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register
rs2 to memory.

===Calling Conventions===
* x0 = zero
* x1 = ra (return address)
* x2 = sp (stack pointer)
* x3 = gp (global pointer)
* x4 = tp (thread pointer) <- Not needed...
* x5-x7 = t0-t2 (temp)
* x8 = s0/fp saved register/frame pointer
* x9 = s1 (saved register)
* x10-x11 = function arguments/return values
* x12-x17 = a2-a7 function arguments <- Don't need this many arguments...
* x18-x27 = s2-s11 saved registers <- Find out what saved are for... Do we need more than x8?
* x28-x31 = t3-6 temporaries <- Don't need these

- Spec 2.1p109

==RV32E==
"For resource-constrained embedded applications, we have defined the RV32E subset, which only has 16 registers (Chapter 3)." - Spec (2.1p10)

"A further simplification is that the counter instructions (rdcycle[h],rdtime[h], rdinstret[h]) are no longer mandatory." - RV32E

"RV32E uses a subset of the Soft-Float calling convention. As only 16 integer registers x0–x15 are
present, there are only six argument registers (x10–x15), two saved registers (x8–x9), and three
temporary registers (x5–x7). The stack is kept aligned on a four-byte boundary."

* x0 = zero
* x1 = ra (return address)
* x2 = sp (stack pointer)
* x3 = gp (global pointer)
* x4 = tp (thread pointer)
* x5-x7 = t0-t2 (temp)
* x8-x9 = s0-s1 (saved registers)
* x10-x15 = Argument registers

==Opcode Flag Bits==
All the 32-bit instructions in the base ISA have their lowest two bits set to 11. The optional compressed 16-bit
instruction-set extensions have their lowest two bits equal to 00, 01, or 10. Standard instruction-
set extensions encoded with more than 32 bits have additional low-order bits set to 1, with the
conventions for 48-bit and 64-bit lengths shown in Figure 1.1. Instruction lengths between 80 bits
and 176 bits are encoded using a 3-bit field in bits [14:12] giving the number of 16-bit words in
addition to the first 5×16-bit words. The encoding with bits [14:12] set to 111 is reserved for future
longer instruction encodings.

For all 16bit instructions, the first 12 bits are something other than 11. Won't save any space, but would allow more instructions in the 16 bit space.

==Op Codes==
<img src="http://linuxgizmos.com/files/riscv_ref_card1.jpg"/>
<img src="http://linuxgizmos.com/files/riscv_ref_card2.jpg"/>


* "All the 32-bit instructions in the base ISA have their lowest two bits set to 11" - Spec
 xxxxxxxxxxxxxxaa 16-bit (aa != 11)
 xxxxxxxxxxxbbb11 32-bit (bbb != 111)
 xxxxxxxxxx011111 48-bit
 xxxxxxxxx0111111 64-bit
 xnnnxxxxx1111111 (80+16*nnn)-bit, nnn != 111
 x111xxxxx1111111 Reserved for ≥192-bits

Table 9.1 on page 53 has the opcodes.
"In the base ISA, there are four core instruction formats (R/I/S/U), as shown in Figure 2.2. All are
a fixed 32 bits in length and must be aligned on a four-byte boundary in memory. An instruction
address misaligned exception is generated on a taken branch or unconditional jump if the target
address is not four-byte aligned." - Spec (2.2)

* R-type

  31        25 24     20 19     15 14  12 11      7 6           0
 +------------+---------+---------+------+---------+-------------+
 | funct7     | rs2     | rs1     |funct3| rd      | opcode      |
 +------------+---------+---------+------+---------+-------------+

* I-type

  31                  20 19     15 14  12 11      7 6           0
 +----------------------+---------+------+---------+-------------+
 | imm                  | rs1     |funct3| rd      | opcode      |
 +----------------------+---------+------+---------+-------------+

* S-type

  31        25 24     20 19     15 14  12 11      7 6           0
 +------------+---------+---------+------+---------+-------------+
 | imm        | rs2     | rs1     |funct3| imm     | opcode      |
 +------------+---------+---------+------+---------+-------------+

* U-type

  31                                      11      7 6           0
 +---------------------------------------+---------+-------------+
 | imm                                   | rd      | opcode      |
 +---------------------------------------+---------+-------------+

<img src="http://i.stack.imgur.com/Gkjuc.png" width="75%"/>
<img src="http://i.stack.imgur.com/IlZmZ.png" width="75%"/>

==Immediate Encoding==
"There are a further two variants of the instruction formats (SB/UJ) based on the handling of
immediates" - Spec 2.3

"The only difference between the S and SB formats is that the 12-bit immediate field is used to encode
branch offsets in multiples of 2 in the SB format. Instead of shifting all bits in the instruction-
encoded immediate left by one in hardware as is conventionally done, the middle bits (imm[10:1]) and sign bit stay in fixed positions, while the lowest bit in S format (inst[7]) encodes a high-order
bit in SB format."

"Similarly, the only difference between the U and UJ formats is that the 20-bit immediate is shifted
left by 12 bits to form U immediates and by 1 bit to form J immediates. The location of instruction
bits in the U and UJ format immediates is chosen to maximize overlap with the other formats and
with each other."

"Integer computational instructions are either encoded as register-immediate operations using
the I-type format or as register-register operations using the R-type format."

==Instructions==
* ADDI adds the sign-extended 12-bit immediate to register rs1. ADDI rd, rs1, 0 is used to implement the MV
rd, rs1 assembler pseudo-instruction.

==Word Size==
* [http://stackoverflow.com/questions/29618439/what-is-the-size-of-integer-in-8-bit-16-bit-32-bit-processors-microcontrollersOn an 8-bit Atmel AVR Arduino, sizeof(int) returns 2 (e.g. 16-bits) when compiled with GCC 4.3.2 (WinAVR 20081205)]
* [http://electronics.stackexchange.com/questions/203252/what-determines-sizeofint int is a C type. The ATMega's have no concept of it, they work only with 8bit bytes (because they have 8bit AVR CPUs).]