RISC-V: Difference between revisions
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==Minimum Sized ISA== |
==Minimum Sized ISA== |
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* 5-Bits specify register. 33 registers (r0 is always 0). 4-bits will get you 16, 3-Bits will get you 8. |
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===Registers=== |
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* R32, 5-Bits specify register. 32 registers |
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* 4-bits will get you 16 (14) |
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* 3-Bits will get you 8 (6) |
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* 2 registers are fixed. R0 is always zero, XLEN-1 (last reg) is PC. |
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===Op Codes=== |
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xxxxxxxxxxxxxxaa 16-bit (aa != 11) |
xxxxxxxxxxxxxxaa 16-bit (aa != 11) |
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xxxxxxxxxxxbbb11 32-bit (bbb != 111) |
xxxxxxxxxxxbbb11 32-bit (bbb != 111) |
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Revision as of 06:54, 2 November 2016
Minimum Sized ISA
Registers
- R32, 5-Bits specify register. 32 registers
- 4-bits will get you 16 (14)
- 3-Bits will get you 8 (6)
- 2 registers are fixed. R0 is always zero, XLEN-1 (last reg) is PC.
Op Codes
- All the 32-bit instructions in the base ISA have their lowest two bits set to 11
xxxxxxxxxxxxxxaa 16-bit (aa != 11) xxxxxxxxxxxbbb11 32-bit (bbb != 111) xxxxxxxxxx011111 48-bit xxxxxxxxx0111111 64-bit xnnnxxxxx1111111 (80+16*nnn)-bit, nnn != 111 x111xxxxx1111111 Reserved for ≥192-bits