RISC-V: Difference between revisions
Jump to navigation
Jump to search
| Line 19: | Line 19: | ||
xnnnxxxxx1111111 (80+16*nnn)-bit, nnn != 111 |
xnnnxxxxx1111111 (80+16*nnn)-bit, nnn != 111 |
||
x111xxxxx1111111 Reserved for ≥192-bits |
x111xxxxx1111111 Reserved for ≥192-bits |
||
<img src="http://i.stack.imgur.com/Gkjuc.png"/> |
|||
<img src="http://i.stack.imgur.com/IlZmZ.png"/> |
|||
===Word Size=== |
===Word Size=== |
||
Revision as of 07:02, 2 November 2016
Minimum Sized ISA
Registers
- R32, 5-Bits specify register. 32 registers
- 4-bits will get you 16 (14)
- 3-Bits will get you 8 (6)
- 2 registers are fixed. R0 is always zero, XLEN-1 (last reg) is PC.
"For resource-constrained embedded applications, we have defined the RV32E subset, which only has 16 registers (Chapter 3)."
Op Codes
- All the 32-bit instructions in the base ISA have their lowest two bits set to 11
xxxxxxxxxxxxxxaa 16-bit (aa != 11) xxxxxxxxxxxbbb11 32-bit (bbb != 111) xxxxxxxxxx011111 48-bit xxxxxxxxx0111111 64-bit xnnnxxxxx1111111 (80+16*nnn)-bit, nnn != 111 x111xxxxx1111111 Reserved for ≥192-bits
