RISC-V: Difference between revisions
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===Op Codes=== |
===Op Codes=== |
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* All the 32-bit instructions in the base ISA have their lowest two bits set to 11 |
* "All the 32-bit instructions in the base ISA have their lowest two bits set to 11" - Spec |
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xxxxxxxxxxxxxxaa 16-bit (aa != 11) |
xxxxxxxxxxxxxxaa 16-bit (aa != 11) |
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xxxxxxxxxxxbbb11 32-bit (bbb != 111) |
xxxxxxxxxxxbbb11 32-bit (bbb != 111) |
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xnnnxxxxx1111111 (80+16*nnn)-bit, nnn != 111 |
xnnnxxxxx1111111 (80+16*nnn)-bit, nnn != 111 |
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x111xxxxx1111111 Reserved for ≥192-bits |
x111xxxxx1111111 Reserved for ≥192-bits |
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"In the base ISA, there are four core instruction formats (R/I/S/U), as shown in Figure 2.2. All are |
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a fixed 32 bits in length and must be aligned on a four-byte boundary in memory. An instruction |
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address misaligned exception is generated on a taken branch or unconditional jump if the target |
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address is not four-byte aligned." - Spec (2.2) |
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<img src="http://i.stack.imgur.com/Gkjuc.png"/> |
<img src="http://i.stack.imgur.com/Gkjuc.png"/> |
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Revision as of 07:04, 2 November 2016
Minimum Sized ISA
Registers
- R32, 5-Bits specify register. 32 registers
- 4-bits will get you 16 (14)
- 3-Bits will get you 8 (6)
- 2 registers are fixed. R0 is always zero, XLEN-1 (last reg) is PC.
"For resource-constrained embedded applications, we have defined the RV32E subset, which only has 16 registers (Chapter 3)."
Op Codes
- "All the 32-bit instructions in the base ISA have their lowest two bits set to 11" - Spec
xxxxxxxxxxxxxxaa 16-bit (aa != 11) xxxxxxxxxxxbbb11 32-bit (bbb != 111) xxxxxxxxxx011111 48-bit xxxxxxxxx0111111 64-bit xnnnxxxxx1111111 (80+16*nnn)-bit, nnn != 111 x111xxxxx1111111 Reserved for ≥192-bits
"In the base ISA, there are four core instruction formats (R/I/S/U), as shown in Figure 2.2. All are a fixed 32 bits in length and must be aligned on a four-byte boundary in memory. An instruction address misaligned exception is generated on a taken branch or unconditional jump if the target address is not four-byte aligned." - Spec (2.2)
