RISC-V: Difference between revisions
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===Immediate Encoding=== |
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"There are a further two variants of the instruction formats (SB/UJ) based on the handling of |
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immediates" - Spec 2.3 |
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"The only difference between the S and SB formats is that the 12-bit immediate field is used to encode |
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branch offsets in multiples of 2 in the SB format. Instead of shifting all bits in the instruction- |
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encoded immediate left by one in hardware as is conventionally done, the middle bits (imm[10:1]) and sign bit stay in fixed positions, while the lowest bit in S format (inst[7]) encodes a high-order |
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bit in SB format." |
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"Similarly, the only difference between the U and UJ formats is that the 20-bit immediate is shifted |
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left by 12 bits to form U immediates and by 1 bit to form J immediates. The location of instruction |
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bits in the U and UJ format immediates is chosen to maximize overlap with the other formats and |
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with each other." |
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"Integer computational instructions are either encoded as register-immediate operations using |
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the I-type format or as register-register operations using the R-type format." |
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===Word Size=== |
===Word Size=== |
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Revision as of 07:13, 2 November 2016
Minimum Sized ISA
Registers
- R32, 5-Bits specify register. 32 registers
- 4-bits will get you 16 (14)
- 3-Bits will get you 8 (6)
- 2 registers are fixed. R0 is always zero, XLEN-1 (last reg) is PC.
"For resource-constrained embedded applications, we have defined the RV32E subset, which only has 16 registers (Chapter 3)." - Spec (2.1p10)
Op Codes
- "All the 32-bit instructions in the base ISA have their lowest two bits set to 11" - Spec
xxxxxxxxxxxxxxaa 16-bit (aa != 11) xxxxxxxxxxxbbb11 32-bit (bbb != 111) xxxxxxxxxx011111 48-bit xxxxxxxxx0111111 64-bit xnnnxxxxx1111111 (80+16*nnn)-bit, nnn != 111 x111xxxxx1111111 Reserved for ≥192-bits
"In the base ISA, there are four core instruction formats (R/I/S/U), as shown in Figure 2.2. All are a fixed 32 bits in length and must be aligned on a four-byte boundary in memory. An instruction address misaligned exception is generated on a taken branch or unconditional jump if the target address is not four-byte aligned." - Spec (2.2)
Immediate Encoding
"There are a further two variants of the instruction formats (SB/UJ) based on the handling of immediates" - Spec 2.3
"The only difference between the S and SB formats is that the 12-bit immediate field is used to encode
branch offsets in multiples of 2 in the SB format. Instead of shifting all bits in the instruction-
encoded immediate left by one in hardware as is conventionally done, the middle bits (imm[10:1]) and sign bit stay in fixed positions, while the lowest bit in S format (inst[7]) encodes a high-order
bit in SB format."
"Similarly, the only difference between the U and UJ formats is that the 20-bit immediate is shifted left by 12 bits to form U immediates and by 1 bit to form J immediates. The location of instruction bits in the U and UJ format immediates is chosen to maximize overlap with the other formats and with each other."
"Integer computational instructions are either encoded as register-immediate operations using the I-type format or as register-register operations using the R-type format."