RISC-V

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Revision as of 07:02, 2 November 2016 by H3g3m0n (talk | contribs) (→‎Op Codes)
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Instructions in binary

Minimum Sized ISA

Registers

  • R32, 5-Bits specify register. 32 registers
  • 4-bits will get you 16 (14)
  • 3-Bits will get you 8 (6)
  • 2 registers are fixed. R0 is always zero, XLEN-1 (last reg) is PC.

"For resource-constrained embedded applications, we have defined the RV32E subset, which only has 16 registers (Chapter 3)."

Op Codes

  • All the 32-bit instructions in the base ISA have their lowest two bits set to 11
xxxxxxxxxxxxxxaa 16-bit (aa != 11)
xxxxxxxxxxxbbb11 32-bit (bbb != 111)
xxxxxxxxxx011111 48-bit
xxxxxxxxx0111111 64-bit
xnnnxxxxx1111111 (80+16*nnn)-bit, nnn != 111
x111xxxxx1111111 Reserved for ≥192-bits

Word Size